Resources

Tech Papers and Data SheetsDynaloy provides expert technical documentation for all of our semiconductor and specialty chemistries products. We understand the specification requirements of our customers. All pertinent information is listed here to provide an outstanding experience when using Dynaloy’s products.

For an overview of semiconductor solutions, view our brochure DYL-011 Photoresist and Residue Removers.

For information on many of our specialty chemistries, view DYL-3277 Specialty Chemistries Solvent Guide.


 

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A New Single Wafer Cleaning Technology for Compound Semiconductor Manufacturing (2012)
We have developed a novel single wafer cleaning technology that targets the needs of compound semiconductor manufacturing: removal of photoresist and post-etch residue while maintaining compatibility with a myriad of compound semiconductor materials, exposed metals, and dielectric layers. The CoatsClean™ platform is a combination of both process and chemical technology featuring significantly reduced chemical usage, short process times, wafer-to-wafer consistency, and process flexibility. In this paper, the CoatsClean™ technology is described and results are shown that demonstrate the capability to remove post-etch residue in the production of GaAs heterojunction bipolar transistors (HBT)s for both polyimide via and base pedestal layers.
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Analysis of Polyimide Passivation Damage in Wafer-Level Removal and Cleaning Processes
Flip Chip (FC) and Wafer Level Packaging (WLP) are two of the fastest growing segments in the IC packaging industry. The practice of incorporating FC or bump technology in devices are experiencing significant growth. The primarily reason for the growth is the improvement that they provide in power and ground distribution with the attendant reduction in SSN (simultaneous switching noise).
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Characterization of Clean after Photoresist Removal from Wafers with Copper Pillars with Lead-Free Solder Caps (2016)
This paper will describe wet cleaning processes used today for copper pillar cleans, with special focus on characterization of the Cu pillar and solder side walls. Examples using several different photoresists and copper and solder configurations will be examined. Samples with differing copper/solder bump heights and pitches will be discussed. Cleaning and compatibility results will be shown.
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Efficient TSV Resist and Residue Removal in 3DIC (2014)
Cleaning following the reactive ion etching (RIE) process has been accomplished historically using an ashing process to remove any remaining photoresist, followed by dipping the wafer in a solution of post-etch residue remover.
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Enabling Cleaning of Cu Pillar Wafers using a Stripper with Improved EHS Profile (2014)
The purpose of this study is to report the cleaning and characterization results after photoresist removal from wafers patterned with copper pillars and lead-free solder caps. Wafer cleaning was accomplished using a photoresist stripper that has an improved HSE profile due to the exclusion of TMAH as a component. This formulation is demonstrated to remove TOK CR4000, a thick spin-on positive resist, with excellent copper compatibility in a single wafer CoatsCleanTM process using an EVG-301RS tool.
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Formulation Development for Bosch Etch Residue Removal: Effect of Solvent on Removal Efficiency (2015)
Originally presented at IMAPS 2015 in Orlando at the 48th Annual International Symposium on Microelectronics, this paper contains the results from a study of solvents that are used to develop formulations to remove Bosch etch residue from TSVs. The selection of components for an etch residue remover must take into consideration removal efficiency, environmental-health-safety (EHS) guidelines, and material cost. The results demonstrate that the solvent selection has a dramatic impact on polymer removal efficiency. Complete residue removal using TMAH-free and NMP-free formulations for TSV diameters down to 5 μm is demonstrated.
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Identifying Defects and Determining Root Causes Found During Thick Photoresist Removal In Lead-Free WLP (2007)
FlipChip (FC) and Wafer Level Packaging (WLP) are two of the fastest growing segments in the integrated circuit (IC) industry. The practice of incorporating FC or bump technology in chips is experiencing significant growth, due to the improvement it provides in power, ground distribution and thermal management. It also results in the attendant reduction of simultaneous switching noise, (SSN).
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New Cleaning Technology Solutions for Lead-Free Micro-Bumping (2011)
Historically, the semiconductor industry has increased performance by decreasing the size of features on chips, thereby improving the cost per performance unit. This has led to the need for the adoption of copper and low-κ dielectric materials to gain improved performance. Being at or near the natural limits for copper presently and with the goals for the industry aggressively continuing to call for reduced energy consumption and smaller form factors, additional approaches need to be considered. One approach, which has garnered a lot of attention, is to re-engineer advanced wafer level packaging (WLP) and develop processes for manufacturing stacked and vertically interconnected device layers.
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Proven Cleaning Technology Solutions for Lead-Free Micro-Bumping Processes (2012)
Opportunities for developing new and enabling packaging schemes are being pursued as part of device improvement strategies for electronic products. Processes such as embedded technologies in wafer level packaging and 3-D chip architecture schemes open up opportunities for realization of a variety of package configurations. As a result, there are many opportunities to impact both device performance and the processes used to create them.
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Removal of Bosch Etch Residue using Dynastrip DL9150 (2014)
The Bosch etch process is a critical process step used to create through silicon vias (TSVs) for 3D integrated circuit manufacturing. During the Bosch etch, a fluoropolymer passivation layer is formed on the sidewall of TSVs to help achieve a vertical profile and to protect the exposed dielectric materials. The fluoropolymer residue on the sidewalls in the TSVs must be removed prior to subsequent process steps
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Removal of JSR THB-S375N Photoresist Using a Photoresist Stripper with an Improved EHS Profile (2013)
Negative liquid photoresist (resist) has been used broadly in wafer bumping for fine pitch bump pitch formation. One of the major challenges in using these resists is effective removal of the resist without leaving organic residue or re-depositing the polymer on the surface during the photoresist strip process.
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Removal of TOK CR4000 Thick Positive Photoresist in a Cu Pillar Bump Process (2013)
The use of Cu pillar technology in bumping applications has increased due to the benefits it provides in a broad range of applications.
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Removing Barriers to All-Wet Single-Wafer Cleans in Packaging-Related Applications (2012)
The use of negative dry film or negative spin-on film photoresist has been very common in semiconductor packaging processes. Film thicknesses ranging from 10μm to 120μm have been incorporated into processes ranging from redistribution to solder bump application.
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Resist Removal Technology For Next Generation 3D Packaging Solutions (2011)
Packaging technologies such as fan out wafer level packaging (FOWLP) and embedded chip in substrate technologies have gained a lot of attention recently from OEMs, OSATS, technology developers, and technology integrators in the integrated circuit (IC) industry as schemes for continuing wafer level chip scale package (WLCSP). Both technologies are focused on incorporating ICs into their packaging platform and on taking advantage of current process recipes and infrastructure as much as possible.
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Single Wafer Cleaning for 3DIC Manufacturing (2014)
3-D integrated circuit (3DIC) manufacturing presents a number of challenges for wafer cleaning that include removal of different types of photoresists and residues and an increasing complexity related to materials compatibility. Materials that need to be removed from wafers during 3DIC manufacturing include photoresist and etch residues.
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Wet Cleaning as an Improved Final Quality Control of DRIE-Produced Features (2015)
With the deep reactive ion etch (DRIE) process, a separate wet cleaning procedure on single wafer or batch systems can help address cost sensitivity concerns while also providing exceptional residue removal. This paper details the results of a collaboration between Dynaloy and Plasma-Therm LLC and shows the effectiveness of a new solvent at removing residual polymer contaminants. The paper also examines the possibility of expanding this application to post-plasma dicing where the wafers are mounted on a tape frame.
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White Ring Defect Formation in Lead-Free Wafer Level Packaging (2006)
FlipChip (FC) and Wafer Level Packaging (WLP) are two of the fastest growing segments in the integrated circuit (IC) packaging industry. The practice of incorporating FC or bump technology in devices is experiencing significant growth, due to the improvement it provides in power and ground distribution, with the attendant reduction in simultaneous switching noise, (SSN).